cross-posted from: https://lemmy.ml/post/44200610

RVA23 profile of RISC-V marks a turning point in how mainstream CPUs are expected to scale performance. By making the RISC-V Vector Extension (RVV) mandatory, it elevates structured, explicit parallelism to the same architectural status as scalar execution. Vectors are no longer optional accelerators bolted onto speculation-heavy cores. They are baseline capabilities that software can rely on.

RVA23 doesn’t force scalar execution to become deterministic. It simply makes determinism viable because the scalar side is no longer responsible for throughput. The vector unit handles the parallel work explicitly, and the scalar core becomes a coordinator that can be simple, predictable, and low‑power without sacrificing performance.

To understand why this shift matters, it helps to recall how thoroughly speculative execution came to dominate high-performance CPU design. It delivered speed, but at increasing cost—in power, complexity, verification burden, and security exposure. RVA23 does not reject speculation. Instead, it restores balance. It acknowledges that predictable, vector-driven parallelism is now a credible, mainstream path for performance growth.

  • Static_Stan@thelemmy.club
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    27 days ago

    Even though RISC-V already managed to produce a few footguns ( like compressed instruction stream), I like it overall. It has became absolute smash arch for microcontrollers and it is rapidly rising elsewhere, from linux SoCs upwards.

    But above all it is becoming the default base for all these exotic and esoteric new branches that Tenstorrent and so many others are going for.

    I’d like to see someone doing smart vector/tensor unit that could do its execution autonomously, once its “shader program” gets filled. And I’d like to see that unit capable of doing its own conditional loops etc while the scalar core goes minding its own business.